ARM System Memory Management Unit Architecture Specification
Document: IHI 0070H.a
Version: SMMUv3.0 / SMMUv3.1 / SMMUv3.2 / SMMUv3.3 / SMMUv3.4 / SMMUv3.5
Copyright: © 2016-2026 Arm Limited or its affiliates
This is a Markdown conversion of the ARM System Memory Management Unit (SMMU) Architecture Specification for online reading and search.
Chapters
| Chapter | Title | Description |
|---|---|---|
| 1 | About this specification | References, terms, scope |
| 2 | Introduction | History, feature versions (v3.0–v3.5), system placement |
| 3 | Operation | Software interface, streams, data structures, translation, queues, caches, security |
| 4 | Commands | Command queue commands (CFGI, TLBI, CMD_SYNC, etc.) |
| 5 | Data structure formats | STE, CD, L1STD, L1CD, event records |
| 6 | Memory map and registers | Full register definitions (SMMU_IDR*, SMMU_CR*, etc.) |
| 7 | Faults, errors and Event queue | Fault model, event record formats, error handling |
| 8 | Page request queue | PRI page request interface |
| 9 | Address Translation Operations | ATOS (Address Translation Operations) |
| 10 | Performance Monitors Extension | PMU counters, events, registers |
| 11 | Debug/Trace | Debug features |
| 12 | RAS | Reliability, Availability and Serviceability |
| 13 | Attribute Transformation | Memory attribute transformation rules |
| 14 | External interfaces | AXI/ACE/CHI interface requirements |
| 15 | Translation procedure | Detailed translation algorithm |
| 16 | System and Implementation Considerations | Integration guidance |
| 17 | MPAM | Memory System Resource Partitioning and Monitoring |
| 18 | MEC | Support for Memory Encryption Contexts |